Design of Optimized Network on-Chip for Reliable Communication
Dr. Jayaprakash. M, JCT College of Engineering and Technology, Coimbatore, Tamil Nadu; Manikandan S ,JCT College of Engineering and Technology, Coimbatore, Tamil Nadu; Pradeep Kumar S ,JCT College of Engineering and Technology, Coimbatore, Tamil Nadu; Sam Jasper P ,JCT College of Engineering and Technology, Coimbatore, Tamil Nadu; Prakash C ,JCT College of Engineering and Technology, Coimbatore, Tamil Nadu
Systems-on-Chip, Multiprocessor Array, Network-on-Chip (Noc), Mesh Type Noc, Virtual Channel
In this paper, a new mesh-typed NoC(Network on Chip) architecture is proposed which aims at enhancing network performance. Networks-on-Chips (NoCs) are a new design paradigm for scalable high throughput communication infrastructures, in Systems-on-Chips (SoCs) with billions of transistors. The idea of NoCs is dividing a chip into several independent clusters connected together by global communication architecture. As the number of cores integrated into System-on-Chip increases, the on-chip communication limits the performance and power consumption in current and next generation SoCs. The resultant NoC uses mesh topology along with virtual channel allocation methodology. The routing algorithm combined with mesh topology improves average latency and saturation traffic load.
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Paper ID: GRDCF007029
Published in: Conference : National Conference on Emerging Trends in Electrical, Electronics and Computer Engineering (ETEEC - 2018)
Page(s): 162 - 166
Published in: Conference : National Conference on Emerging Trends in Electrical, Electronics and Computer Engineering (ETEEC - 2018)
Page(s): 162 - 166