Article

K.Brindha , Arasu Engineering College; R.Christy ,; S.Indhu ,; J.Madhubala ,; P.Sathyaraj ,

In conventional technology, CMOS logic circuits are used. This technology suffer from high power issues due to long traffic delay and leakage current. After that, Hybrid logic-in memory architecture using Magnetic Tunnel Junction(MTJ) to overcome these limitations. Magnetic Tunnel junction is a non-volatile device to achieve high access speed and infinite endurance. Recently, 1-bit non-volatile full adder using MTJ have been proposed to build low-power high- density arithmetic/logic unit for processor. However, this method has partial non-volatile property because MTJ is used as one of their operands. For this purpose, extending 1-bit to multi bit structure offers full non-volatility. Synchronous 8-bit non-volatile full adder presented in this paper, the input signals are stored in MTJ instead of CMOS register. MTJ with CMOS logic circuits three possible structures are proposed with respect to different location of NV data. The design is simulated in 180nm CMOS technology using cadence EDA tool.