Analysis of Carry Select Adder using Different Logic Styles

Fincy Mol F, Prince Shri Venkateshwara Padmavathy Engineering College; Saranya Tv ,Prince Shri Venkateshwara Padmavathy Engineering College; Shalini M ,Prince Shri Venkateshwara Padmavathy Engineering College

Fast Arithmetic Operations, Ladner-Fischer, Minimum Logic Depth

Carry Select Adder (CSLA) is one of the fastest adder used to perform fast arithmetic operations. In our project, a modified carry select adder is designed by using single Ladner-Fischer (LF) and binary to Excess-1 Converter (BEC) instead of using dual RCA’s to reduce the area and delay. The correct sum and carryout signals will be selected by a set of multiplexers. LF adder is a parallel prefix form of carry look-ahead adder (CLA). It is the fastest adder with focus on time and is the common choice for high performance adders in industry. The better performance of LF adder is because of its minimum logic depth and bounded fan-out. In the proposed CSLA, one ripple carry adder (RCA) fed with Cin=0 is replaced by LF adder. The performance of proposed CSLA is analyzed and compared against CSLA design using RCA and BEC. The number of gates used in proposed CSLA is fewer than the CSLA using RCA and BEC. The result shows that area of proposed method is reduced by 25% and delay is reduced by 14%.
    [1] Pakkiraiah Chakali, Madhu Kumar Patnala, “Design of high speed Ladner Fischer based carry select adder”, International Journal of soft computing and engineering (IJSCE), ISSN: 2231-2307, vol-3, issue-1, pp.173-176, March 2013. [2] N.Vijaya Bala and T.S. Saravana kumar,”Area minimization of carry select adder using boolean algebra”, International journal of advances in engineering and technology, ISSN: 22311963,vol.6,issue 3, pp.1250-1255, July 2013. [3] Woopyo jeong, Kaushik roy and Cheng-kok koh,”High performance low power carry select adder using dual transition skewed logic”. [4] Senthil kumar.A and Kousalya devi.A, “VLSI implementation of efficient carry select adder architecture”, International journal of advance research in science and engineering IJARSE, vol.No.2, Issue No.4,pp 88-93, April 2013. [5] Yuke Wang, C.Pai and Xiaoyu Song, “Design of hybrid carry look ahead/ carry select adders”, IEEE transactions on circuits and system-2: analog and digital signal processing, vol.49, no.1, January 2002, pp.16-24. [6] Gangandeep Singh and Chakshu Goel,”design of low power and efficient carry select adder using 3-T XOR Gate”, Hindawi publishing corporation advances in electronics, Article Id 564613,pp.1-6, Volume 2014. [7] Laxman Shanigarapu and Bhavana P. Shrivastava,”Low power and high speed carry select adder”, International Journal of scientific and research publications, Vol .3, Issue 8, ISSN 2250-3153,pp.1-9, Aug 2013. [8] B.Ramkumar and Harish M Kittur, “Low power and area efficient carry select adder”, IEEE transaction on very large scale integration (VLSI) systems, vol.20, no.2, pp.371-375, February 2012. [9] N Dhanunjaya Rao and Ashok Kumar, “FPGA implementation of high performance carry select adder”, international journal of advanced research in electronics and communication Engineering (IJARECE), volume 1, issue 6,pp.58-64, Dec 2012. [10] Sarabdeep Singh and dilip kumar,”Design of area and power efficient modified carry select adder “, International Journal of computer applications (0975-8887), volume 33-no.3, Nov 2011. [11] Sun yan, Zhang xin and Jin xi,” Low-power Carry Select Adder Using Fast All-one Finding Logic”. [12] Gyanesh Savita, Vijay Kumar Magraiya, Gajendra Kulshrestha and Vivek Goyal, “Designing of low power 16-bit carry select adder with less delay in 45nm CMOS process technology”, International Journal of Emerging Techno logy and Advanced Engineering, ISSN 2250-2459, ISO 9001:2008, volume 3, Issue 7, pp.250-252,July 2013. [13] Lakshmanan, Ali Meaamar and Masuri Othman,” High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm”,IEEE, 2006, pp.598-602. [14] Amita P. Thankare, Saurabh Agrawal and Vibha Tiwari, “32 bit carry select adder with BEC-1 technique” Proceedings of Sixth IRAJ International Conference, 6th October 2013, Pune, India. ISBN: 978-93-82702-32-0, pp. 127-132. [15] Yajuan He. Chip Hong Chang and Jiangmin Gu, “An area efficient 64-bit square root carry select adder for low power applications”, IEEE, 2005, pp.40824085. [16] Salivahana and Arivazhagan, “Digital Electronics”, third edition. [17] G.A.Ruiz and M.Granda,”An area efficient static CMOS carry select adder based on a compact carry look ahead unit”, microelectronics journal 35, 2004, pp. 939-944.
Paper ID: GRDJEV02I090025
Published in: Volume : 2, Issue : 9
Publication Date: 2017-09-01
Page(s): 12 - 18