Data-Driven Design and Validation Techniques in Advanced Chip Engineering

Abstract

On-chip self-test (CST) has gained attention as a cost-effective approach for testing sophisticated integrated circuits (IC). In contrast to conventional test methods involving expensive automatic test equipment (ATE) for off-chip test sequence generation and application. CST requires low hardware overhead; test sequence generation; data generation, storage, compression, and analysis; and user-friendly software for diagnosis, which requires sophisticated design techniques. With growing design complexity, the need for faster signal propagation leads to higher parasitic capacitance (C) and resistance (R) on the chip. As a result, parasitic (or coupled) capacitance between nets and substrate should be estimated during early physical design phases. Embedded tools for RC parasitic extraction should be customized based on the design specifications at different abstraction levels.

In this case, detailed capacitance extraction is performed using verification software. Capacitance is usually the only parasitic that has to be extracted and accounted for in simulations and validation, as the resistance is estimated and not included in the extraction files. It emphasizes estimation of parasitic capacitance for an IC design – from the circuit netlist through to final layout. Several examples from custom digital designs are shown, detailing both strategy and methodology. It is Canonical-XML (CXML)-based physical design database developed for the NP-complete placement optimization problem. OpAmp without blind test structure. A capacitance extraction and estimation method is developed to provide the design with a comprehensive physical realization scenario