Design and Analysis of Different Circuits using DCVSL & Static CMOS Technique

Aradhana Pathak, Buddha Institute of technology; Mr. Narendra Chaurasiya ,

CMOS, DCVSL, Magnitude Comparator, EXOR Gate, VLSI, Tanner EDA

The basic requirement of any Integrated Circuit is high speed and low power processing of the data signals to perform the desired execution. The minimization of feature size plays an important role in increasing the performance of integrated circuits. However, the minimization of ICs has affect on leakage current when compared to the total current requirement of the circuit. So in this work presents the design of single bit magnitude comparator & 3 input EXOR gate using conventional CMOS logic style as well as DCVSL style. Then, the comparison has been carried out for both the designs with some parameters. These parameters are power dissipation, delay and how much transistors have been used in the respective designs, and then concluded that which design yields best results accordingly. In CMOS circuits, as the technology scales down to nano scale, the sub-threshold leakage current increases with the decrease in the threshold voltage. So we need a technique to tackle the power dissipation problem in CMOS circuits do the analysis keeping parameters such as power consumption, delay, voltage & transistor count. First, there is the analysis between power consumption & delay, keeping the voltage constant at 5V. We here can see that circuit of the DCSVL structures produces better results in terms of power consumption by lowering its value. The circuit designed using DCVS Logic style is an attempt to further reduce the power dissipation with minimum delay.
    [1] C. Piguet, Low-Power CMOS Circuits, CRC Press, 2006. [2] L. Bisdounis,D. Gouvetas, andO. Koufopavlou, “A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits,” International Journal of Electronics, vol. 84, no. 6, pp. 599–613, 1998. [3] R. Faghih Mirzaee, T. Nikoubin, K. Navi, and O. Hashemipour, “Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic,” Microelectronics Journal, vol. 44, no. 12, pp. 1238–1250, 2013. [4] Priyanka and A. K. Singh, “A low voltage high speed DCVSL based ring oscillator,” in Proceedings of the Annual IEEE India Conference (INDICON ’15), pp. 1–5, New Delhi, India, December 2015. [5] D. W. Kang and Y.-B. Kim, “Design of enhanced differential cascode voltage switch logic (EDCVSL) circuits for high fan-in gate,” in Proceedings of the 15th Annual IEEE International ASIC/SOC Conference (ASIC/SOC ’02), pp. 309–313, September 2002. [6] N. Hanchate and N. Ranganathan, “LECTOR: a technique for leakage reduction in CMOS circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 196-205, 2004. [7] P. Lakshmikanthan and A. Nu˜nez, “A novel methodology to reduce leakage power in differential cascode voltage switch logic circuits,” in Proceedings of the 3rd International Conference on Electrical and Electronics Engineering, pp. 1–4, Veracruz, Mexico, September 2006. [8] W. Chen, W. Hwang, P. Kudva, G. D. Gristede, S. Kosonocky, and R. V. Joshi, “Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design,” in Proceedings of the International Symposium on Low Electronics and Design (ISLPED ’01), pp. 263–266, August 2001. [9] John P. Uyemura, (2002) Introduction to VLSI Circuits and Systems, John Wiley & Sons. [10] H.T. Bui, Y. Wang and Y. Jiang, ―Design and analysis of low-power 10-transister full adders using XOR-XNOR gates, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, Vol. 49, no. 1, pp. 25- 30, Jan. 2002. [11] K. Navi, O. Kaehi, M. Rouholamini, A. Sahafi, S.Mehrabi, N. Dadkhahi, ―Low power and High performance 1-bit CMOS fill adder for nanometer design, IEEE computer Society Annual Symposium VLSI (ISVLSI), Montpellier fr, 2008, pp. [12] Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, (2011) ―New Design Methodologies for High-Speed Low-Voltage 1 Bit CMOS Full Adder Circuits,‖ Journal of Computer Technology and Application, Vol. 2, No. 3, pp. 190-198. [13] Sumeer Goel, Mohammed A. Elgamel, Magdy A. Bayoumi, Yasser Hanafy, (2006) Design Methodologies for High-Performance Noise-Tolerant XOR-XNOR Circuits, IEEE Transactions on Circuits and Systems- I, Vol. 53, No. 4, pp. 867-878. [14] Design of Energy efficient Full adder using hybrid CMOS logic style Mohammad Shamim Imtiaz, Md Abdul Aziz Suzon, Mahmudur Rahman, International Journal of Advances in Engineering & Technology, Jan 2012. [15] Subodh Wairya , Garima Singh, Vishant, R. K. Nagaria and S. Tiwari (2011), ―Design Analysis of XOR (4T) based Low Voltage CMOS Full Adder Cell, In Proceeding of IEEE International Conference on Current Trends In Technology (NUiCONE‘11), Ahmedabad, India pp. 1-7. [16] Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari Comparative Performance Analysis of XOR/XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design, International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012. [17] Avireni Srinivasulu and Madugula Rajesh, “ULPD and CPTL Pull-Up Stages for Differential Cascode Voltage Switch Logic”, Hindwai Publishing Corporation, Journal of Engineering, Volume 2013, Article ID 595296, pp.1-5. [18] L. G. Heller and W. R. Griffin, “Cascode voltage switch logic: A differential CMOS logic family,” in ISSCC Dig. Tech. Papers, 1984, pp. 16-17. [19] R. K. Montoye, “Testing scheme for differential cascode voltage switch circuits,” IBM Tech. Disc. Bull., vol. 27, pp. 6148-6152, 1985.
Paper ID: GRDJEV03I070045
Published in: Volume : 3, Issue : 7
Publication Date: 2018-07-01
Page(s): 13 - 19