Implementation of Fault Tolerant FIR Filter for Digital Communication Systems
Jyotishma Bharti, Integral University; Tarana Afrin Chandel ,Integral University
Error Correction Codes (ECC), Digital Signal Processing (DSP), Finite Impulse Response (FIR) Parallel FIR, Very Large Scale Integration (VLSI).
A realistic communication system is not free from noise. So the transmission of information through may rather be corrupted by noise in the channel. Therefore it is necessary for every communication systems to have suitable means to recognize and correct those errors in the information received over communication channels. There are various types of filters are used by Digital signal processing (DSP) applications. In which digital parallel FIR filters are very widely used in numerous application. Over the years, many implementation techniques of digital FIR filter for DSP application has exploit the various practical difficulties such as low speed, high delay and above of all fault tolerance. Due to the VLSI complexity scaling, there are many complex systems that embed with many filters. The filters operations in those complex systems are usually parallel. As filters is the unit that comes in any type of communication system ranging from simple voice data to complex real time data conversation. So it is then mandatory to implement some technique that shows the fault tolerance achieved in parallel filters. In this paper we are implementing the FIR Filter with 6-bit Fault tolerant using BCH codes. The complete design has been developed by VHDL and synthesize and simulated by XILINX ISE Tool.
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Paper ID: GRDJEV02I090023
Published in: Volume : 2, Issue : 9
Publication Date: 2017-09-01
Page(s): 5 - 11
Published in: Volume : 2, Issue : 9
Publication Date: 2017-09-01
Page(s): 5 - 11