Implementation of a General Purpose Sorter on FPGA
Mr.Kamel AliKhan Siddiqui, Deccan College of Engineering and Technology
Digital Algorithm Model & FPGA Implementation, using Xilinx, Finite State Machine for Controller and Design of the Data Path Structure of the Filter
The objective of the paper is to implement a general purpose sorting algorithm. The paper should offer a sorting network that can be deployed in various applications in impulsive noise reduction filters for image processing and other signal processing applications. The algorithm and sorting network should offer less hardware complexity and better memory usage options. It involves design, simulation and FPGA implementation of a general purpose sorter processor. The paper describes a detailed survey of sorting algorithms that are acquiescent to FPGA implementation, homing in on the most suitable one that may be deployed in digital signal and image processing applications. The work extends by demonstrating the potential of the implemented sorter in noise reduction filters.
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Paper ID: GRDJEV02I010046
Published in: Volume : 2, Issue : 1
Publication Date: 2017-01-01
Page(s): 44 - 50
Published in: Volume : 2, Issue : 1
Publication Date: 2017-01-01
Page(s): 44 - 50