Design of 32 Bit Vedic Multiplier using Carry Look Ahead Adder

Divya. K, P.S.R. Rengasamy College of Engineering for Women, Sivakasi, Tamil Nadu; Surya. K ,P.S.R. Rengasamy College of Engineering for Women, Sivakasi, Tamil Nadu; Uma Narayani. R ,P.S.R. Rengasamy College of Engineering for Women, Sivakasi, Tamil Nadu; Vidhiya. B ,P.S.R. Rengasamy College of Engineering for Women, Sivakasi, Tamil Nadu; Sathya. G ,P.S.R. Rengasamy College of Engineering for Women, Sivakasi, Tamil Nadu

Vedic Multiplier, Carry Look Ahead Adder

The digital architecture is mainly used in all type of real world application architectures and thus the architecture modify based on enhancement purpose. The VISI is to optimize the any type of digital architecture. Multiplication is an important fundamental function in arithmetic logic operation. Computational performance of a DSP system is limited by its multiplication performance and since, multiplication dominates the execution time of most DSP algorithms. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculation based on 16 Sutras. Our work is to develop the 32 –bit Vedic multiplier architecture using carry look ahead adder technique.
    [1] Suganthi Venkatachalam and Seok – Burn Ko, IEEE JOURNAL”Design of Power and Area Effcient Approximate Multiplier December 2016”. [2] P. Ram Sirisha, Dr.A.M. Prasad, IEEE JOURNAL“Design and Performance Analysis of 32 bit Array Multiplier using optimized Carry Select Adder September 2015”. [3] Anushukhare Ashish, Raghwanshiruchi Gupta, IEEE JOURNAL“Vedic ALU using Area optimized Urdhva Triyambakam Multiplier 2014”. [4] Pratisha Rai, Shailendra Kumar, Prof.(Dr.) S.H. Saeed, IEEE JOURNAL“Design of floating point multiplier using Vedic Aphorims 2014”. [5] Sudhanshu Shekhar Pandey, Amit Bakshi, Vikash Sharma, IEEE JOURNAL“128 bit Low Power and Area Efficient Carry Select Adder May 2013”. [6] N. Vijayabala and T.S. Saravana Kumar, IEEE JOURNAL “Area minimization of Carry Select Adder using Boolean algebra July 2013”. [7] T. Ratna Mala, R. Viney Kumar, T. Chandra Kala, IEEE JOURNAL “Design and Verification of Area efficient High Speed Carry Select Adder November 2012”. [8] S. Ramachandran, Kirti. S. Pande , IEEE JOURNAL“Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture 2012”. [9] Rangharajan Vemkatesan, Amit Agarwal, Kaushik Roy and Anand Raghunathan, IEEE JOURNAL “Modeling and Analysis of circuits for Approximate Computing 2011”. [10] C.N. Marimuthu, Dr.P.Thangaraj, Aswathy Ramesan, IEEE JOURNAL“Low Power Shift and ADD Multiplier Design June 2010”.
Paper ID: GRDCF007018
Published in: Conference : National Conference on Emerging Trends in Electrical, Electronics and Computer Engineering (ETEEC - 2018)
Page(s): 95 - 99