Design of Energy Efficient Approximate Multiplier
J. Gayathri, SCAD Institute of Technology, Palladam, India; S. Sowmiya ,SCAD Institute of Technology, Palladam, India; S. K. Soundriya Leela ,SCAD Institute of Technology, Palladam, India; S. Bhavatharani ,SCAD Institute of Technology, Palladam, India
Approximate Computing, Gates, Error Analysis
Multiplier is one of the arithmetic operations that are used in VLSI circuits. Approximate multiplier is designed by using half adder, full adder and 4-2 compressor. Approximate multiplier is used to reduce the logic gate count, power consumption, delay and it provides high speed output. Area and speed of approximate multiplier is efficient than the conventional multipliers. This adder is mainly used in DSP Application, Image Processing. The simulation result shows the low power consumption by using Xilinx ISE simulation tool.
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Paper ID: GRDCF007013
Published in: Conference : National Conference on Emerging Trends in Electrical, Electronics and Computer Engineering (ETEEC - 2018)
Page(s): 67 - 72
Published in: Conference : National Conference on Emerging Trends in Electrical, Electronics and Computer Engineering (ETEEC - 2018)
Page(s): 67 - 72