Archive

Publication for Volume-2 Issue-9, August 2017

Title
:
Mineral Content Seaweed Gracilaria Verrucosa Fertilized using Vermicompost
Article Type
:
Research Article
Author Name(s)
:
Andi Rahmad Rahim, Department of Aquaculture, Faculty of Agriculture, University of Muhammadiyah, Gresik, East Java, In; Rajuddin Syamsuddin ,Department of Aquaculture University of Hasanuddin, Makassar, South Sulawesi. ; Khusnul Yaqin ,Department of Water Resources Management University of Hasanuddin, Makassar, South Sulawesi.
Country
:
Indonesia
Research Area
:
Aquaculture Development
Seaweed as chlorophyll plants requires nutrients to support growth. Vermicompost is 100% organic fertilizer quality and environmentally friendly, contains of various nutrients needed for seaweed to grow and produce optimal levels of agar and play an important role in stimulating the vegetative growth of seaweed. The purpose of this study is to determine the optimal dose of vermicompost fertilizer to produce the content of mineral elements such as NO3, NH4, PO4, SO4 and Mg seaweed. From the results of the Kolmogorov Smirnov (KS) and Shapiro-Wilk (SW) norms, the mineral content of seaweed in the form of nitrate (NO3), ammonium (NH4), phosphate (PO4) and sulfate (SO4) spread following normal distribution (p> 0.05). Levene homogenity test of mineral content of NO3, NH4, PO4 and SO4 have the same homogenity has been fulfilled (p> 0.05). The mineral content of nitrate (NO3), phosphate (PO4), magnesium (Mg) and sulfate (SO4) seaweed Gracilaria verrucosa the highest obtained in treatment A and the lowest in treatment F while the highest mineral content of ammonium (NH4) seaweed at treatment C and the lowest on the treatment F (without fertilizer).
Keywords : Gracilaria Verrucosa, Vermicompost Fertilizer, Nitrate, Ammonium, Phosphate, Magnesium, Sulfate
[1]	Patadjai, R., S. (2007). Production Growth and Quality of Seaweed Kappaphycus alvarezii (Doty) Doty on Different Cultivation Habitats. Graduate program. Hasanuddin University. Makassar.
[2]	Lazcano C, Brandon. MG, Dominiguez J. (2008). Comparison of the Effectiveness of Composting and Vermicompost for the Biological Stabilization of Cattle Manure. Chemosphere. 72 : 1013-1019.
[3]	AOAC, (1995). Official Methods of Analyses. Washington, DC: AOAC.
[4]	Alamsjah, MA, SIlviana, IN., Rachmawati K. (2009). Influence of Combination of Compost Fertilizer and NPK on Growth, Number of Chlorophyll a and Water Content. Faculty of Fisheries and Marine University of Airlangga. Surabaya.
[5]	Wang, C.F., Li, J.S., Wang, L.J. dan Sun, X.Y. (2008). Influence of NaOH Concentrations on Synthesis of Pure-form Zeolite A from Fly Ash Using Two-Stage Method. Journal of Hazardous Materials. Vol. 155, hal. 58–64.
[6]	Domininguez, J., Edward, CA, Subler, S. (1997). A comparation of vermicomposting and composting. Bio Cycle 38:57-59.
[7]	Sharma, S., Pradhan, K., Satya, S., Vasudevan, P. (2005). Potentiality of Earthworms for Waste Management and in Other Uses. J American Sci 1:4-16.
[8]	Marsono. (2001). Root Fertilizer. Penebar Swadaya. Jakarta.
Title
:
Implementation of Fault Tolerant FIR Filter for Digital Communication Systems
Article Type
:
Research Article
Author Name(s)
:
Jyotishma Bharti, Integral University; Tarana Afrin Chandel ,Integral University
Country
:
India
Research Area
:
electronics
A realistic communication system is not free from noise. So the transmission of information through may rather be corrupted by noise in the channel. Therefore it is necessary for every communication systems to have suitable means to recognize and correct those errors in the information received over communication channels. There are various types of filters are used by Digital signal processing (DSP) applications. In which digital parallel FIR filters are very widely used in numerous application. Over the years, many implementation techniques of digital FIR filter for DSP application has exploit the various practical difficulties such as low speed, high delay and above of all fault tolerance. Due to the VLSI complexity scaling, there are many complex systems that embed with many filters. The filters operations in those complex systems are usually parallel. As filters is the unit that comes in any type of communication system ranging from simple voice data to complex real time data conversation. So it is then mandatory to implement some technique that shows the fault tolerance achieved in parallel filters. In this paper we are implementing the FIR Filter with 6-bit Fault tolerant using BCH codes. The complete design has been developed by VHDL and synthesize and simulated by XILINX ISE Tool.
Keywords : Error Correction Codes (ECC), Digital Signal Processing (DSP), Finite Impulse Response (FIR) Parallel FIR, Very Large Scale Integration (VLSI).
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[3]	N. Kanekawa, E. H. Ibe, T. Suga and Y. Uematsu, Dependability in Electronic Systems: Mitigation of Hardware Failures, Soft Errors, and ElectroMagnetic Disturbances, New York, NY, USA: Springer Verlag, 2010.
[4]	M. Nicolaidis, “Design for soft error mitigation,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 405–418, Sep. 2005.
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[6]	A. Reddy and P. Banarjee “Algorithm-based fault detection for signal processing applications,” IEEE Trans. Comput., vol. 39, no. 10, pp. 1304– 1308, Oct. 1990.
[7]	T. Hitana and A. K. Deb, “Bridging concurrent and non-concurrent error detection in FIR filters,” in Proc. Norchip Conf., 2004, pp. 75–78.
[8]	Y.-H. Huang, “High-efficiency soft-error tolerant digital signal processing using finegrain sub word-detection processing,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 18, no. 2, pp. 291–304, Feb. 2010.
[9]	Yu-Chi Tsao and Ken Choi, 2012. “Area- Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm” IEEE transactions on very large scale integration (vlsi) systems, vol. 20, no. 2, feb. 2012.
[10]	Yu-Chi Tsao and Ken Choi, 2011. “Hardware- Efficient Parallel FIR Digital Filter Structures For Symmetric Convolutions “978-1-4244-9474- 3/11/$26.00 ©2011 IEEE.
[11]	Lavina Magdalene Mary “Area Efficient Parallel Fir Digital Filter Structures Based On Fast Fir Algorithm” Vol. 3, Issue 1, January –February 2013, pp.2042-2046
[12]	D. A. Parker and K. K. Parhi, 1997. “Lowarea/ power parallel FIR digital filter implementations,” J. VLSI Signal Process.Syst., vol. 17, no. 1, pp. 75–92, 1997.
[13]	K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.
[14]	J. G. Chung and K. K. Parhi, 2002. “Frequency spectrum- based low-area low-power parallel FIR filter design,” EURASIP J. Appl. Signal Process., vol. 2002, no. 9, pp. 444–453, 2002.
[15]	Alfredo Rosado-Muñoz and Manuel Bataller- Mompeán,“FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches,”vol.58, no.3, Mar.2011.
[16]	Z.-J. Mou and P. Duhamel, 1991. “Short-length FIR filters and their use in fast non recursive filtering,” IEEE Trans. Signal Process., vol. 39, no.6, pp. 1322–1332, Jun. 1991.
[17]	C. Cheng and K. K. Parhi, 2004. “Hardware efficient fast parallel FIR filter structures based on iterated short convolution,” IEEE Trans.
Title
:
Analysis of Carry Select Adder using Different Logic Styles
Article Type
:
Reveiw Article
Author Name(s)
:
Fincy Mol F, Prince Shri Venkateshwara Padmavathy Engineering College; Saranya Tv ,Prince Shri Venkateshwara Padmavathy Engineering College; Shalini M ,Prince Shri Venkateshwara Padmavathy Engineering College
Country
:
India
Research Area
:
VLSI
Carry Select Adder (CSLA) is one of the fastest adder used to perform fast arithmetic operations. In our project, a modified carry select adder is designed by using single Ladner-Fischer (LF) and binary to Excess-1 Converter (BEC) instead of using dual RCA’s to reduce the area and delay. The correct sum and carryout signals will be selected by a set of multiplexers. LF adder is a parallel prefix form of carry look-ahead adder (CLA). It is the fastest adder with focus on time and is the common choice for high performance adders in industry. The better performance of LF adder is because of its minimum logic depth and bounded fan-out. In the proposed CSLA, one ripple carry adder (RCA) fed with Cin=0 is replaced by LF adder. The performance of proposed CSLA is analyzed and compared against CSLA design using RCA and BEC. The number of gates used in proposed CSLA is fewer than the CSLA using RCA and BEC. The result shows that area of proposed method is reduced by 25% and delay is reduced by 14%.
Keywords : Fast Arithmetic Operations, Ladner-Fischer, Minimum Logic Depth
[1]	Pakkiraiah Chakali, Madhu Kumar Patnala, “Design of high speed Ladner Fischer based carry select adder”, International Journal of soft computing and engineering (IJSCE), ISSN: 2231-2307, vol-3, issue-1, pp.173-176, March 2013.
[2]	N.Vijaya Bala and T.S. Saravana kumar,”Area minimization of carry select adder using boolean algebra”, International journal of advances in engineering and technology, ISSN: 22311963,vol.6,issue 3, pp.1250-1255, July 2013.
[3]	Woopyo jeong, Kaushik roy and Cheng-kok koh,”High performance low power carry select adder using dual transition skewed logic”.
[4]	Senthil kumar.A and Kousalya devi.A, “VLSI implementation of efficient carry select adder architecture”, International journal of advance research in science and engineering IJARSE, vol.No.2, Issue No.4,pp 88-93, April 2013.
[5]	Yuke Wang, C.Pai and Xiaoyu Song, “Design of hybrid carry look ahead/ carry select adders”, IEEE transactions on circuits and system-2: analog and digital signal processing, vol.49, no.1, January 2002, pp.16-24.
[6]	Gangandeep Singh and Chakshu Goel,”design of low power and efficient carry select adder using 3-T XOR Gate”, Hindawi publishing corporation advances in electronics, Article Id 564613,pp.1-6, Volume 2014.
[7]	Laxman Shanigarapu and Bhavana P. Shrivastava,”Low power and high speed carry select adder”, International Journal of scientific and research publications, Vol .3, Issue 8, ISSN 2250-3153,pp.1-9, Aug 2013.
[8]	B.Ramkumar and Harish M Kittur, “Low power and area efficient carry select adder”, IEEE transaction on very large scale integration (VLSI) systems, vol.20, no.2, pp.371-375, February 2012.
[9]	N Dhanunjaya Rao and Ashok Kumar, “FPGA implementation of high performance carry select adder”, international journal of advanced research in electronics and communication Engineering (IJARECE), volume 1, issue 6,pp.58-64, Dec 2012.
[10]	Sarabdeep Singh and dilip kumar,”Design of area and power efficient modified carry select adder “, International Journal of computer applications (0975-8887), volume 33-no.3, Nov 2011.
[11]	Sun yan, Zhang xin and Jin xi,” Low-power Carry Select Adder Using Fast All-one Finding Logic”.
[12]	Gyanesh Savita, Vijay Kumar Magraiya, Gajendra Kulshrestha and Vivek Goyal, “Designing of low power 16-bit carry select adder with less delay in 45nm CMOS process technology”, International Journal of Emerging Techno logy and Advanced Engineering, ISSN 2250-2459, ISO 9001:2008, volume 3, Issue 7, pp.250-252,July 2013.
[13]	Lakshmanan, Ali Meaamar and Masuri Othman,” High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm”,IEEE, 2006, pp.598-602.
[14]	Amita P. Thankare, Saurabh Agrawal and Vibha Tiwari, “32 bit carry select adder with BEC-1 technique” Proceedings of Sixth IRAJ International Conference, 6th October 2013, Pune, India. ISBN: 978-93-82702-32-0, pp. 127-132.
[15]	Yajuan He. Chip Hong Chang and Jiangmin Gu, “An area efficient 64-bit square root carry select adder for low power applications”, IEEE, 2005, pp.40824085.
[16]	Salivahana and Arivazhagan, “Digital Electronics”, third edition.
[17]	G.A.Ruiz and M.Granda,”An area efficient static CMOS carry select adder based on a compact carry look ahead unit”, microelectronics journal 35, 2004, pp. 939-944.
Title
:
Power Gating Techniques for Nano-Scale Devices
Article Type
:
Research Article
Author Name(s)
:
Srujan Tirupathi, Punjab Central University; Praveen Nimmagadda ,Punjab Central University
Country
:
India
Research Area
:
Nanotechnology
Power consumption is one of the major issues in CMOS technology. ITRS reports that leakage power may dominate the total power consumption. As technology feature size shrinks, the static power dominates the dynamic power consumption. This is known as the sub-threshold leakage which rises by creating a weak inversion channel between drain and source. Gate oxide thickness reduces as technology decreases which increases the sub-threshold leakage. Along with sub-threshold leakage there is an increase in ground bounce noise. This paper reviews different stacking techniques proposed in other papers. But each of those papers had certain trade-offs. So, a combination of the existing techniques has been implemented to have minimal sub-threshold leakage, ground bounce noise and propagation delay
Keywords : CMOS Nanoscale, Subthreshold Leakage, Stacking Transistors, Ground Bounce Noise
[1]	S. Poduri, M. Dutta, and M. Stroscio, "Characterization of CdS Nanowires Self-Assembled in a Nanoporous Alumina Template," Journal of electronic materials, vol. 43, p. 3979, 2014.
[2]	Parag Barua, “A Novel architecture for nanometer scale low power VLSI design”.
[3]	M. Mazouchi, S. Poduri, and M. Dutta, "Growth and Characterization of Indium Oxide, Zinc Oxide and Cadmium Sulfide Nanowires by Vapor-Liquid-Solid Growth Technique," Applied Physics Research, vol. 6, p. 55, 2014.
[4]	K. Xu, M. Purahmad, K. Brenneman, X. Meshik, S. Farid, S. Poduri, et al., "Design and Applications of Nanomaterial-Based and Biomolecule-Based Nanodevices and Nanosensors," in Design and Applications of Nanomaterials for Sensors, J. M. Seminario, Ed., ed Dordrecht: Springer Netherlands, 2014, pp. 61-97.
[5]	S. Poduri, M.S Choi, Mitra Dutta and M. Stroscio, "Numerical analysis of electric field enhancement in ZnO film with plasmonic au quantum dots," in IEEE International Workshop Conference of Computational Electronics, 2015.
[6]	J. M. Seminario, Design and Applications of Nanomaterials for Sensors vol. 16: Springer, 2014.
[7]	S. Farid, X. Meshik, M. Choi, S. Mukherjee, Y. Lan, D. Parikh, et al., "Detection of Interferon gamma using graphene and aptamer based FET-like electrochemical biosensor," Biosensors and Bioelectronics, vol. 71, pp. 294-299, 2015.
[8]	Souvik Mukherjee, Xenia Meshik, Min Choi, Sidra Farid,, Debopam Datta, Yi Lan, Shripriya Poduri, Ketaki Sarkar, Undarmaa Baterdene, Ching-En Huang,, Yung Yu Wang, Peter Burke, Mitra Dutta, Michael A. Stroscio, "A Graphene and Aptamer Based Liquid Gated FET-Like Electrochemical Biosensor to Detect Adenosine Triphosphate," IEEE Transactions on NanoBioscience, vol. 14, pp. 967 - 972, 2015.
[9]	K. L. Brenneman, S. Poduri, M. A. Stroscio, and M. Dutta, "Optical detection of lead (II) ions using DNA-based nanosensor," IEEE Sensors Journal, vol. 13, pp. 1783-1786, 2013.
[10]	IWolfgang Arden et.al. “More-than-Moore” White Paper,International Technology Roadmap for Semiconductors.
[11]	Low-Leakage and Compact Registers with Easy-Sleep Mode, Journal of Low Power Electronics.
[12]	Sleepy Keeper: a New Approach to Low- leakage Power VLSI Design Vincent J. Mooney III.
[13]	Dual Threshold Transistor Stacking (DTTS) - A Novel Technique for Static Power Reduction in Nanoscale Cmos Circuits.
Title
:
Active and Passive Learning: A Comparison
Article Type
:
Research Article
Author Name(s)
:
Shreyasi Shubhendu Paul, SavitribaiPhule Pune University, PES’s Modern College of Engineering,Pune
Country
:
India
Research Area
:
E-Learning, Learning Management System
The purpose of the paper is to identify learning points and inspirations from two different approaches by survey and a comparison.
Learners learning completed by selecting (Active Learning) and receiving (Passive Learning) information. But which Learning style or process is meet learners expectation?
The main purpose of this paper is to study, analyze, and explore for the right decision while choosing learning style to meet the requirements of Learners. I done a comparison of Active and Passive Learning to help to adapt learning style with respect to different conditions. Comparison done with both teacher and student point of view.
Keywords : Active Learning, Passive Learning, Learning styles, Learning ways, Learning Processes.
Basic
[1]	Kyle MacDonald, Michael C. Frank,“When does passive learning improve the effectiveness of active learning?”CogSci 2016 papers.
[2]	Dr.Oluwatomi M. Alade1 and Mrs Angela C. Ogbo2,“A Comparative Study of Chemistry Students’ Learning Styles Preferences in Selected Public and Private Schools in Lagos Metropolis”,IOSR Journal of Research & Method in Education (IOSR-JRME) e-ISSN: 2320–7388,p-ISSN: 2320–737X Volume 4, Issue 1 Ver. I (Jan. 2014), PP 45-53.
[3]	Shaoming Lu, Hui-shu Zhang,“A comparative study of education for sustainable development in one British university and one Chinese university”,IJSHE15,1.
[4]	Michael Prince, “Does Active Learning Work? A Reviewof the Research”,J Engr. Education, 93(3), 223-231 (2004).
[5]	Ho Van Han, M. A.,”A SURVEY OF ENGLISH MAJOR JUNIORS' ACTIVE VERSUS PASSIVE LEARNING STYLES AT BVU”,International Journal of Information Research and Review Vol. 2, Issue, 03, pp. 553-555 March, 2015.
[6]	Paras Minhas, Arundhati Ghosh (2012).” The effects of passive and active learning on student preference and performance in an undergraduate basic...”. Article in Anatomical Sciences Education • July 2012.
Website References
[7]	https://cei.umn.edu/support-services/tutorials/what-active-learning/elements-active-learning
[8]	https://en.wikipedia.org/wiki/Active_learning
[9]	https://www.openlearning.com/blog/HowPeopleLearnActiveVsPassiveLearning
[10]	https://onlinelearninginsights.wordpress.com/tag/passive-vs-active-learning/
[11]	http://www4.ncsu.edu/unity/lockers/users/f/felder/public/Papers/Prince_AL.pdf
[12]	http://www.crlt.umich.edu/tstrategies/tsal
[13]	http://digital.nsta.org/publication/?i=221015&article_id=1783528&view=articleBrowser&ver=html5#{"issue_id": 221015,"view":"articleBrowser","article_id":"1783528"}
[14]	https://en.wikipedia.org/wiki/Passive_learning
[15]	https://en.wikipedia.org/wiki/Active_learning
[16]	http://citt.ufl.edu/online-teaching-resources/activelearning/active-vs-passive-learning-in-online-courses/
[17]	http://www.csun.edu/science/ref/pedagogy/active-passive/active-passive-learning.html
Title
:
Pocket Transitional Manager
Article Type
:
Other
Author Name(s)
:
Jayasheela D K, KLE Institute of Technology, Hubballi; Jayasheela D K ,KLE Institute of Technology, Hubballi; Sudha Gidamallanavar ,KLE Institute of Technology, Hubballi
Country
:
India
Research Area
:
Computer Engineering
The Pocket Transitional Manager application is built on android platform. This app is for maintaining records of expense and balance information. The balance amount is that hard cash i.e. how much you amount you are having in your hand that amount is added into balance. The expense is that how much amount you are spending on different items. This app provide functionalities like adding expense details, adding balance amount, displays expense amount and expense list, displays balance amount and added balance amount, adding images of bills which related to the expense details, creating backup files of expenses and imported if they are deleted and so on. The each functionality requires the different activity where the required data to be inputted and the results are achieved. The user will add the expense details like category and amount how much it cost and the date is recorded in the expense list from the expense activity. The expense list is displayed and it can be displayed based on the date which user requires. The expenses are not only added or displayed but the information about the total expense amount and the remaining amount is displayed and this information is shared from one user to other. The user can add or view the images of bills from the image gallery. The balance amount is added and viewed by the user. 
Keywords : Expense, Balance, Categories, Images, Backup
[1]	Francois Andry, Lin Wan and Daren Nicholson,” A Mobile Application Accessing Patients’ Health Records Through A Rest API”, HEALTHINF 2011 - International Conference on Health Informatics.
[2]	Neelakandan.B, Duraisekar. S, Balasubramani.R, Srinivasa Ragavan.S, “Implementation of Automated Library Management System in the School of Chemistry Bharathidasan University using Koha Open Source Softwa”, INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No1, 2010
[3]	Doc. Ing. Naqib Daneshjo, “PRODUCTION MANAGEMENT SYSTEMS”, Transfer inovácií 28/2013.
Reference Links
[4]	www.developer.android.com
[5]	www.mysqltutorial.org
Title
:
Dynamic Analysis of Multi Storied Building with and without Shear Wall and Bracing
Article Type
:
Case Study
Author Name(s)
:
Sanjeev, Veerappa Nisty Engineering Collage Shorapur; Prof. Lokesh. G ,Veerappa Nisty Engineering Collage Shorapur; Prof. Sahebgouda Patil ,Veerappa Nisty Engineering Collage Shorapur; Dr. Lingaraj Shastri ,Veerappa Nisty Engineering Collage Shorapur
Country
:
India
Research Area
:
Shorapur
Now a day the number of buildings are constructed and designed on the basis of architectural requirement and aesthetic view. Most of buildings are constructed in some spatial configuration like X shape, V shape with x and y co-ordinates non parallel to the structure. Earthquake is causing more damage to different configuration of building and their main problem is in the slenderness ratio. The main goal of this project is to make a comparative study of dynamic behavior of buildings with different configuration of structure in all seismic zones and different types of soils. In this study, a spatial configuration structure of 20stories up to 70m height of each storey height of 3.5m, with Shear wall and bracing at a different location in building is considered. The dynamic behavior of the building in all seismic zones II, III, IV, V and on different types of soil say hard, medium and soft soil was studied .The structure has outer periphery beams carrying R.C Shear wall of 200 mm thickness. The response spectrum analysis was carried out by using software of ETAB’s version 9.7.4.considering bracing and shear wall at a different location in the building. The following seismic parameters were analyzed and the behavior of the structure was studied in detail. 
Keywords : Plan, Etab, Analysis of Building
[1]	“Dynamic Response of High Rise Structures Under the Influence of Shear Walls” Syed Khasim Mutwalli and Dr. Shaik Kamal Mohammed Azam (2015).
[2]	“Comparative Study On Seismic Analysis Of Multistorey Building Stiffened With Bracing And Shear Wall”. Mohd atif and prof. Laxmikant vairagade (2015).
[3]	“Effect of Wind Load on High Rise Structure” Shraddha J. Patil and R. S. Talikoti (2014).
[4]	Multi-Criteria Spatial Analysis of Building Layouts- nagara@hope.ac.uk (2014).
[5]	“Seismic Behaviour of Multistorey Shear Wall Frame versus Braced Concrete Frames” S.R. Thorat and P.J. Salunke (2015).
[6]	”Effect Of Different Infill Material On The Seismic Behaviour Of High Rise Building With Soft Storey: - Poonam patil and D.B.kulkarni (2015).
[7]	“Seismic Forces and its Behaviour” Abhijeet bairikar and kanehan kanagali (2014).
[8]	“Seismic Behaviour of Multi-Storey Shear Wall Frame Versus Braced Concrete Frames (ijrte)” sandeep r. thorat, p.j.salunke (2013).
[9]	“Dynamic Response of High Rise Structures Under the Influence of Shear Walls” Syed Khasim Mutwalli (2014).
[10]	“A Study of the Various Structural Framing Systems Subjected to Seismic Loads” Abhyuday Titiksh1, Dr. M.K. Gupta (2015).
[11]	“Effect of Configuration on Lateral Displacement and Cost of the Structure for high rise steel space frames Subjected to Wind loads”J.Renuka and M.Pavan kumar (2015).
[12]	“Seismic Analysis of RCC Building with and without Shear wall” P.P Chandurakar and Dr.P.S.Pajgade (2013).
[13]	“Comparative Study of Strength of RC Shear Wall at Different Location on Multi-Storied Residential Building” Varsha R and Harne (2014).
[14]	“Seismic Comparative Study of Multistoried R.C.C Building With Shear Wall in Bare Frame and Masonry Infill Frame for Various Types of Soil and Seismic Zones” Ghalimath A.G, Waghmare Y.M, Zadbuke A.A and Chaudhari A.RI2015).
[15]	“Seismic Response of RC Framed Building” Verma S.K, Roshan Lal and Raman kumar(2014)
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